clock rate
英 [klɒk reɪt]
美 [klɑːk reɪt]
时钟同步频率
双语例句
- An obvious solution is to use a processor with a faster clock rate, but for any given technology there exists a physical limit where the clock simply can't go any faster.
一个明显的解决方案是使用具有更快时钟频率的处理器，但是对于任何特定技术来讲都存在一个物理极限，时钟频率也有这样的极限。 - The clock ticks at a rate of about one mutation every two years.
这种时钟周期以每两年发生一次突变的速度为基准。 - In the hardware, the clock circuit is designed, and the baud rate is configured.
电抗值，电阻（率）硬件方面设计了时钟电路和波特率配置； - Planck black body spectrum claims transitivity of clock rate synchronization being equivalent to zeroth law
普朗克黑体谱要求钟速同步的传递性等价于第零定律 - There are constraints on the CPU clock speed related to the baud rate.
波特率会对CPU时钟速度产生限制。 - The clock offset and frequency drift rate for sensor nodes are estimated and then compensated by using the time-stamp recorded in two adjacent synchronizations.
该算法利用连续两次同步过程中所记录的时间信息来估算节点时钟的偏移和频率漂移率，并进行补偿。 - The number of stages completed each second is given by the so-called clock rate.
每秒所完成的步骤数目用所谓的时钟频率来表示。 - Some major puzzles in black hole theory and General Relativity, including Hawking radiation, information puzzle, singularity theorem and synchronization of clock rate, are presented.
介绍了黑洞理论和广义相对论中的几个重要疑难，涉及霍金辐射、信息佯谬、奇性定理和钟速同步，并给出了可能的解答。 - In particular, they used a molecular clock rate derived from invertebrates, which is slower than the one based on vertebrates.
特别的是，他们使用从无脊椎动物推衍出的分子时钟，速度比脊椎动物的分子时钟要快得多。 - The high frequency clock allows for a greater sampling rate, which results in higher accuracy and faster signal processing capability.
高频时钟可支持更高的取样率，从而达到更高的精确度和更快的信号处理能力。 - The relation between the synchronization of clock rate and the zeroth law of thermodynamics, and the relation between the singularity theorem and the third law of thermodynamics are pointed out.
指出了钟速同步与热力学第零定律的关系，以及奇性定理与热力学第三定律的关系。 - The simulation and synthesis show that the design has 96 Mb/ sec encryption/ decryption rate under the 17.14 MHZ system clock rate.
仿真和综合结果表明该模块在17.14MHz的时钟频率下可达到96Mb/sec的加/解密速率。 - Clock rate measurement via GMS
通过GMS的钟速测量 - A new synthesis method of baseband echo power spectrum, which adopts Direct Digital Synthesis ( DDS) technology, reduces greatly the clock rate and data memory.
采用直接数字合成（DDS）技术，提出了新的基带回波功率谱的合成方法，显著降低了基带信号合成的时钟频率和数据存储容量。 - It is estimated that a data and clock recovery module with a higher operating rate is available only if some devices are changed.
可以预计，只要在器件上作某些更换，亦可制成工作速率更高的时钟数据恢复模块。 - Then, using the constant rate of clock in inertial system, the un constant rate of clock made by existence of inertial field is proved.
利用惯性系时间的均匀性，证明了非惯性系中因惯性场的存在而造成的时间非均匀性。 - Both instructional and functional simulation for the whole VSP show that this motion estimation coprocessor works correctly with other functional components of VSP under the system clock rate up to 80 MHz.
目前，已经通过VSP芯片整体的指令级与功能级仿真与验证。结果表明，当系统时钟为80MHz时，运动估计协处理器与VSP的其它功能部件及指令部件可以有机协调地工作。 - The correlate analysis of the industry cesium clock rate change resulted from the ion pump parameter
工业铯钟速率随离子泵参数变化的相关分析 - It is discussed that the suitable measurements of reliability of atomic clock are the conditional failure rate function Z ( t) and the corresponding half-life statistic.
本文讨论了原子钟可靠性的适用测量是条件故障率函数Z（t）和相应的半寿命统计。 - To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.
从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。 - The sampling time of the receiver might miss the best decision point when sampling clock is fixed and rate of sampling is limited. Under this circumstances, symbol decision is affected badly by ISI.
在采样时钟固定且采样速率受限的情况下接收机的采样时刻不一定在信号的最佳判决点，此时码元判决受ISI影响较为严重。 - The paper desc-ibes the principle of experiment and gives some preliminary results of clock synchronization, especially for clock rate ( frequency) measurement by time difference.
本文叙述了实验原理，给出了钟同步、特别是通过时刻差进行钟速（频率）测量的一些初步结果。 - The method is a fully-digitized process at the sampling clock rate, so that it can be conveniently implemented by FPGA or DSP, whose synchronization precision can reach 1% of the sampling interval.
该方法是一种基于信号采样时钟速率的全数字化处理过程，其同步精度可达到信号采样间隔的1%以上，且便于FPGA或DSP实现。 - Thus the support can be given to a timing requirement which is at task level and is of microsecond precision while the μ C/ OS-ⅱ remains to be in original clock rate; the precision of the time response of system can be greatly improved.
从而，使μC/OSⅡ在原有时钟节拍不变的基础上，提供对微秒级精度的任务级定时请求的支持，大幅度提高系统时间响应的准确性。 - Application of the technology of sampling in different phase in clock circuit realizes maximum 200M equivalent sampling rate of timing analyzer.
在时钟电路中采用分相采样技术，实现了定时分析最高200M的等效采样速率。 - With the zero-th law of thermodynamics equivalent to the transitivity of clock rate synchronization, the above-mentioned conclusion can also be obtained.
并运用热力学第零定律等价于钟速同步的传递性的论断讨论了上述结论。 - Estimation of species divergence times is well known to be sensitive to violation of the molecular clock assumption ( rate constancy over time).
众所周知，物种分化年代的估计对分子钟（进化速率恒定）假定很敏感。 - Because of the limits of feedback devices, high speed pseudo noise code generation cannot depend simply on the improvement of clock rate.
由于反馈器件的限制，高速伪码不能采用单独依赖提高时钟频率的方法。 - With the rapidly increase of the clock frequency and data rate, the signal integrity issues of the PCB are becoming more and more serious.
随着数字电路中时钟和数据频率的不断提高，PCB的信号完整性问题越来越突出。